library ieee;
use ieee.std_logic_1164.all;

entity div25MHz is
port (	clk50MHz :  in std_logic;
	clk25MHz : out std_logic);
end entity div25MHz;

architecture behavior of div25MHz is
signal state : std_logic :='0';
begin
	clk25MHz<=state;
	
	process (clk50MHz) is
	begin
		if clk50MHz'event and clk50MHz='1' then
			state <= not state;
		end if;
	end process;

end architecture behavior;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity myRAM is 
port (
 AddrWr  :  in std_logic_vector (2 downto 0); --Dirección de escritura
 AddrRd  :  in std_logic_vector (2 downto 0); --Dirección de lectura
 clkWr	 :  in std_logic;
 clkRd	 :  in std_logic;
 dataIn  :  in std_logic_vector (3 downto 0); --Registro de entrada
 dataOut : out std_logic_vector (3 downto 0)	 --Registro de salida
 wrEn	 :  in std_logic);			 --Habilitacion de escritura: '0' no escribe, '1' escribe
);
end entity myRAM;

architecture behavior of myRAM is
type matrix is array (0 to 7) of std_logic_vector (3 downto 0);
signal       memory : matrix;
attribute  ramstyle : string;
attribute  ramstyle of memory : signal is "M-RAM";
signal    dataInBuf : std_logic_vector (3 downto 0);
signal AddressWrite : std_logic_vector (2 downto 0);
signal  AddressRead : std_logic_vector (2 downto 0);
begin

	--Acceso de escritura
	process (clkWr)
	begin
		if (clkWr'event and clkWr='1' and wrEn='1') then
			   dataInBuf <= dataIn;
			AddressWrite <= AddrWr;
			memory(to_integer(unsigned(AddressWrite)))<=dataInBuf;
		end if;		
	end process;	
	
	--Acceso de lectura
	process (clkRd)
	begin
		if (clkRd'event and clkRd='1') then
			AddressRead <= AddrRd;
			dataOut<=memory(to_integer(unsigned(AddressRead))); 
		end if;	
	end process;

end architecture behavior;