library ieee;
use ieee.std_logic_1164.all;
entity contador_moore is
port (
clk : in std_logic;
S : in std_logic;
G : out std_logic_vector (1 downto 0));
end entity contador_moore;
architecture behavior of contador_moore is
signal Qk : std_logic_vector (1 downto 0):="00";
signal Qk_1: std_logic_vector (1 downto 0);
begin
Qk_1 <= "01" when (Qk="00" and S='0') else
"10" when (Qk="01" and S='0') else
"11" when (Qk="10" and S='0') else
"00" when (Qk="11" and S='0') else
"01" when (Qk="00" and S='1') else
"11" when (Qk="01" and S='1') else
"10" when (Qk="11" and S='1') else
"00" when (Qk="10" and S='1');
G <= Qk;
regD: process (clk)
begin
if (clk'event and clk='1') then
Qk <= Qk_1;
end if;
end process regD;
end architecture behavior;
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